1. Field of the Invention
The present invention relates to a processor having an interface with a bus arbitration circuit and a data processing apparatus using the same.
2. Description of the Related Art
FIG. 8 shows a prior art data processing apparatus consisting of a microprocessor 10, a buss master 20, for example, a DMA controller, a memory 21 and an external bus 22 connected therebetween. FIG. 9 is a timing chart showing arbitrating signals of a bus ownership between the microprocessor 10 and the bus master 20. An asterisk `*` attached to reference character for signal means that the signal is active when it is low.
The bus master 20 makes the bus request signal *BREQ low when it is going to use the external bus 22. In response thereto, the microprocessor 10 relinquishes the external bus 22 by setting the output of the microprocessor 10, to which the external bus 22 is connected, to a high impedance state after the microprocessor 10 completes execution of its present instruction, and make an acknowledge signal *BACK high to give the bus master 20 notice of the bus master 20 having being relinquished. In response thereto, the bus master 20 accesses the contents of the memory 21. Upon completion of the access, the bus master 20 relinquishes the external bus 22 by setting the output of the bus master 20, to which the external bus 22 is connected, to a high impedance state and make the bus request signal *BREQ high to give the microprocessor 10 notice of the bus master 20 having being relinquished.
Even if a memory 23 is connected to the microprocessor 10 via an external bus 24 independent of the external bus 22, operation of the microprocessor 10 stops accessing while the acknowledge signal *BACK is low. Therefore, the microprocessor 10 can not get access to the memory 23, and the throughput of a data processing apparatus is lowered. In order to improve the throughput, if bus arbiter regarding the external bus 24 is performed, the control and configuration of the microprocessor 10 becomes complicated.